Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2008-03-20
2009-12-15
Auduong, Gene N. (Department: 2827)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185180, C365S185230
Reexamination Certificate
active
07633804
ABSTRACT:
Memory devices and methods of operating memory devices are provided. In one such embodiment a programming voltage pulse or an erase voltage pulse is applied to memory cells of a memory device. A number of the memory cells that failed to program or erase is determined and is compared to a certain number that can be different than a number of memory cells to be programmed or erased. The programming voltage pulse or the erase voltage pulse is adjusted in response to the comparison of the number of memory cells that failed to program or erase to the certain number. The adjusted programming voltage pulse or the adjusted erase voltage pulse is applied to the memory cells that failed to program or erase.
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patent: 2009/0073772 (2009-03-01), Ha
K. Suh, et al. “A 3.3 V 32 Mb NAND Flash Memory with Incremental Step Pulse Programming Scheme” IEEE Journal of Solid-State Circuits, vol. 30, No. 11, Nov. 1995 pp. 1149-1156.
Auduong Gene N.
Leffert Jay & Polglaze P.A.
Micro)n Technology, Inc.
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