Network device/CPU interface scheme

Details Network device/CPU interface scheme Network device/CPU interface scheme

2003-10-02

2009-08-04

Vaughn, Jr., William C (Department: 2444)

Electrical computers and digital processing systems: multicomput

Multicomputer data transferring via shared memory

C709S250000, C711S153000

Reexamination Certificate

active

07571216

ABSTRACT:
A system and method for implementing a CPU/Network Device Interface that reduces the CPU involvement in managing the interface. New data structures in shared memory that are either read-only or write-only by CPU allow the CPU to efficiently utilize techniques such as write-posting and cache prefetching. Additionally, hardware-assisted packet transmission and high-level packet flow control reduce the burden on the CPU. A fair allocation system assures fair access to the receive interface by multiple line cards.

REFERENCES:
patent: 6094729 (2000-07-01), Mann
patent: 6279052 (2001-08-01), Upadrastra
patent: 6876653 (2005-04-01), Ambe et al.
patent: 6912637 (2005-06-01), Herbst
patent: 7020133 (2006-03-01), Zhao et al.
patent: 7289443 (2007-10-01), Costello
patent: 2002/0174252 (2002-11-01), Hayter et al.
patent: 2002/0174255 (2002-11-01), Hayter et al.
patent: 2003/0099254 (2003-05-01), Richter
“I/O Control Block Rings”, retrieved from the internet Oct. 9, 2003: <http://www.cs.wpi.edu/˜claypool/mqp/raid/html
ode56.html>.
Broadcom Corporation,BCM 1250 Product Brief, copyright 2002 by Broadcom Corporation, Irvine, California.

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