Data register with efficient erase, program verify, and...

Details Data register with efficient erase, program verify, and... Data register with efficient erase, program verify, and...

2006-06-08

2009-08-25

Mai, Son L (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185210, C365S189050, C365S205000

Reexamination Certificate

active

07580291

ABSTRACT:
A programmable memory device circuit comprising a sense and programming circuit, a latch circuit, a verify circuit for coupling the latch circuit logic value to a shared indicator line, and a direct memory access circuit coupled to the verify circuit. The DMA circuit couples a bit line to the verify circuit, and the verify circuit couples the direct memory access circuit to a shared verify indicator and DMA line.

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