Non-volatile semiconductor memory device

Details Non-volatile semiconductor memory device Non-volatile semiconductor memory device

2006-09-08

2009-10-27

Nguyen, Dang T (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185330, C365S185170

Reexamination Certificate

active

07609558

ABSTRACT:
A non-volatile semiconductor memory device includes a memory cell array having a plurality of multi-level memory cells connected in series. The plurality of multi-level memory cells forms a plurality of threshold distributions each of which corresponds to a status of a lower bit and a status of an upper bit, wherein a lower bit and an upper bit constitute a lower page and an upper page respectively. The status of the lower bit dichotomizes the threshold distributions into two groups and the status of the upper bit further dichotomizes each of two groups. When programming a memory cell of the upper page, higher potentials are applied to a non-selected word line adjacent to the selected word line than those applied to the non-selected word line when programming the memory cell of the lower page.

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