Minimum delay high speed bus driver

Details Minimum delay high speed bus driver Minimum delay high speed bus driver

1985-08-26

1987-08-11

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307270, 307246, 307571, H03K 1902, H03K 17687, H03K 1756

Patent

active

046863966

ABSTRACT:
A minimum delay, high speed, tri-state bus driver is utilized to couple data and control signals to a memory bus with a minimum amount of buffering. Two transistors 24, 26, utilized in a bootstrap configuration, deliver a system clock to the gate terminals of output transistors 28, 30 which are coupled to the memory bus 40. The input data signals and accompanying control signals are applied to these bootstrap transistors 24, 26 via push/pull amplifiers 20, 22 and, depending on the data level of the input data signal, either a logic 1, a logic 0, or a high impedance open circuit is applied to the bus.

REFERENCES:
patent: 3922566 (1975-11-01), Kodama et al.
patent: 4029971 (1977-06-01), Pryor
patent: 4280065 (1981-07-01), Mihato et al.
patent: 4417162 (1983-11-01), Keller et al.
patent: 4504745 (1985-03-01), Spence et al.

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