Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
2006-12-29
2008-11-18
Lindsay, Jr., Walter L (Department: 2812)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S510000, C257SE27112, C257SE29345
Reexamination Certificate
active
07453135
ABSTRACT:
Plural trench isolation films are provided with portions of an SOI layer interposed therebetween in a surface of the SOI layer in a resistor region (RR) where a spiral inductor (SI) is to be provided. Resistive element are formed on the trench isolation films, respectively. Each of the trench isolation films includes a central portion which passes through the SOI layer and reaches a buried oxide film to include a full-trench isolation structure, and opposite side portions each of which passes through only a portion of the SOI layer and is located on the SOI layer to include a partial-trench isolation structure. Thus, each of the trench isolation films includes a hybrid-trench isolation structure.
REFERENCES:
patent: 6452249 (2002-09-01), Maeda et al.
patent: 6635550 (2003-10-01), Houston
patent: 6833602 (2004-12-01), Mehta
patent: 2002/0036335 (2002-03-01), Minami
patent: 2002/0072161 (2002-06-01), Maeda
patent: 2002/0171120 (2002-11-01), Maeda et al.
patent: 2002/0190349 (2002-12-01), Maeda et al.
patent: 2003/0008472 (2003-01-01), Yoshimura et al.
patent: 2005/0133864 (2005-06-01), Iwamatsu et al.
patent: 2006/0270126 (2006-11-01), Iwamatsu et al.
patent: 2007/0105329 (2007-05-01), Iwamatsu et al.
patent: 1329367 (2002-01-01), None
patent: 9-289324 (1997-11-01), None
patent: 2000-21902 (2000-01-01), None
patent: 2002-110908 (2002-04-01), None
U.S. Appl. No. 11/617,936, filed Dec. 29, 2006, Iwamatsu et al.
Yuuichi Hirano, et al., “Impact of 0.10 μm SOI CMOS with Body-Tied Hybrid Trench Isolation Structure to Break Trough the Scaling Crisis of Silicon Technology”, IEDM, 2000, pp. 1-4.
Toshiaki Iwamatsu, et al., “Low-Noise and High-Frequency 0.10 μm body-tied SOI-CMOS Technology with High-Resistivity Substrate for Low-Power 10Gbps Netwok LSI”, SSDM, 2003, pp. 1-2.
U.S. Appl. No. 11/873,907, filed Oct. 7, 2007, Iwamatsu et al.
Ipposhi Takashi
Iwamatsu Toshiaki
Lindsay, Jr. Walter L
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Renesas Technology Corp.
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