Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive...
Reexamination Certificate
2004-12-08
2008-11-04
Monbleau, Davienne (Department: 2813)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Reexamination Certificate
active
07446015
ABSTRACT:
A semiconductor device includes a circuit formation region which is formed in a semiconductor substrate and includes a plurality of element formation regions surrounded by isolation regions, respectively. A stress effect relief region of a predetermined width is formed around the circuit formation region to relieve a stress effect of the isolation regions on the operation characteristics of elements formed in the element formation regions and a plurality of dummy features are formed in the stress effect relief region and other part of the circuit formation region than the element formation regions at predetermined distances, the dummy features having the same composition as the element formation regions and predetermined planar dimensions. The predetermined planar dimensions of the dummy features are defined by longitudinal and transverse dimensions most frequently found in the plurality of element formation regions formed in the circuit formation region or selected dimensions of the element formation regions. The predetermined distances between the dummy features are specified as the minimum allowable value in respect of the manufacture of the elements.
REFERENCES:
patent: 6809582 (2004-10-01), Morimoto et al.
patent: 6992392 (2006-01-01), Mori
patent: 9-107028 (1997-04-01), None
patent: 2003-188280 (2003-07-01), None
Okuno Yasutoshi
Yamada Masaru
Harrison Monica D
Matsushita Electric - Industrial Co., Ltd.
McDermott Will & Emery LLP
Monbleau Davienne
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