Semiconductor constructions

Details Semiconductor constructions Semiconductor constructions

2005-11-22

2008-11-18

Pham, Thanhha (Department: 2813)

Active solid-state devices (e.g., transistors, solid-state diode

Regenerative type switching device

Combined with field effect transistor

C257S302000, C257SE27057

Reexamination Certificate

active

07453103

ABSTRACT:
The invention includes semiconductor structures having buried silicide-containing bitlines. Vertical surround gate transistor structures can be formed over the bitlines. The surround gate transistor structures can be incorporated into memory devices, such as, for example, DRAM devices. The invention can be utilized for forming 4F2DRAM devices.

REFERENCES:
patent: 4549927 (1985-10-01), Goth et al.
patent: 5013680 (1991-05-01), Lowrey et al.
patent: 5071782 (1991-12-01), Mori
patent: 5122848 (1992-06-01), Lee et al.
patent: 5278438 (1994-01-01), Kim et al.
patent: 5574299 (1996-11-01), Kim
patent: 5576567 (1996-11-01), Mori
patent: 5874760 (1999-02-01), Burns, Jr. et al.
patent: 5909618 (1999-06-01), Forbes et al.
patent: 5929477 (1999-07-01), Burns, Jr. et al.
patent: 5963469 (1999-10-01), Forbes
patent: 5977579 (1999-11-01), Noble
patent: 5990509 (1999-11-01), Burns, Jr. et al.
patent: 6034389 (2000-03-01), Burns, Jr. et al.
patent: 6072209 (2000-06-01), Noble et al.
patent: 6096598 (2000-08-01), Furukawa et al.
patent: 6114725 (2000-09-01), Furukawa et al.
patent: 6133105 (2000-10-01), Chen et al.
patent: 6150687 (2000-11-01), Noble et al.
patent: 6159789 (2000-12-01), Chuang et al.
patent: 6184091 (2001-02-01), Gruening et al.
patent: 6191470 (2001-02-01), Forbes et al.
patent: 6218236 (2001-04-01), Economikos et al.
patent: 6355520 (2002-03-01), Park et al.
patent: 6399979 (2002-06-01), Noble et al.
patent: 6440801 (2002-08-01), Furukawa et al.
patent: 6498062 (2002-12-01), Durcan et al.
patent: 6504210 (2003-01-01), Divakaruni et al.
patent: 6537870 (2003-03-01), Shen
patent: 6555862 (2003-04-01), Mandelman et al.
patent: 6579759 (2003-06-01), Chudzik et al.
patent: 6593613 (2003-07-01), Alsmeier et al.
patent: 6696746 (2004-02-01), Farrar et al.
patent: 6717205 (2004-04-01), Gratz
patent: 6844591 (2005-01-01), Tran
patent: 7071043 (2006-07-01), Tang et al.
patent: 7122425 (2006-10-01), Chance et al.
patent: 7214621 (2007-05-01), Nejad et al.
patent: 7244659 (2007-07-01), Tang et al.
patent: 7262089 (2007-08-01), Abbott et al.
patent: 7282401 (2007-10-01), Juengling
patent: 7285812 (2007-10-01), Tang et al.
patent: 7349232 (2008-03-01), Wang et al.
patent: 7384849 (2008-06-01), Parekh et al.
patent: 2003/0001200 (2003-01-01), Divakaruni et al.
patent: 2004/0113207 (2004-06-01), Hsu et al.
patent: PCT/US2005/006211 (2005-02-01), None
Lattice Press “Silicon Processing for The VLSI Era, vol. 2: Process Integration” Stanley Wolf, Ph.D. (1990).

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