Dynamic frequency divider with improved leakage tolerance

Details Dynamic frequency divider with improved leakage tolerance Dynamic frequency divider with improved leakage tolerance

2005-06-28

2008-11-18

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Frequency or repetition rate conversion or control

C327S212000, C327S202000, C377S047000

Reexamination Certificate

active

07453294

ABSTRACT:
A dynamic frequency divider circuit with improved leakage tolerance supports a wide frequency range. During the evaluation phase, (1) the input signals can be prevented from changing states, (2) the leakage can be reduced, or (3) both can be implemented to generate the correct output signals. In a architecture-level approach, two dynamic flip-flops can be coupled together. In a circuit-level approach, the dynamic flip-flop can include (1) two additional clocked PMOS transistor added to the inputs of the dynamic flip-flop, or (2) two additional pull-up PMOS transistors to counteract the subthreshold leakage in the NMOS transistors.

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Kaushik Roy et al., “Leakage Current Mechanisms and Leakage Reduction Techniques in Deep-Submicrometer CMOS Circuits,” Proceedings of The IEEE, vol. 91, No. 2, pp. 305-327, Feb. 2003.

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