Test mode circuit and reset control method therefor

Details Test mode circuit and reset control method therefor Test mode circuit and reset control method therefor

2005-11-29

2008-11-11

To, Tuan C (Department: 3663)

Data processing: vehicles, navigation, and relative location

Vehicle control, guidance, operation, or indication

Vehicle diagnosis or maintenance indication

C714S734000, C323S282000, C323S351000, C324S426000, C324S527000

Reexamination Certificate

active

07451025

ABSTRACT:
A power control circuit is provided in a vehicle control ECU mounted in a vehicle. The control circuit, when making a shift to a test mode by a test mode circuit, closes a relay to supply a power voltage from a battery to a power line in the similar manner as an ignition main switch is turned on. A logic circuit section of the test mode circuit is reset by an OR logic of a set level of a test terminal and a level of the power line.

REFERENCES:
patent: 4449100 (1984-05-01), Johnson et al.
patent: 4615318 (1986-10-01), Imoto et al.
patent: 4667176 (1987-05-01), Matsuda
patent: 4749873 (1988-06-01), Mutoh et al.
patent: 5304979 (1994-04-01), Lima et al.
patent: 5726573 (1998-03-01), Chen et al.
patent: 6236219 (2001-05-01), Morgan
patent: 6240534 (2001-05-01), Nakane
patent: 6400195 (2002-06-01), Bhaskaran
patent: 6526536 (2003-02-01), Chen et al.
patent: 7023731 (2006-04-01), Hamaguchi et al.
patent: 2003/0141873 (2003-07-01), Bolz
patent: 2003/0151313 (2003-08-01), Nakanishi
patent: 2004/0095164 (2004-05-01), Kernahan et al.
patent: 2004/0095179 (2004-05-01), Eliason
patent: 2004/0122565 (2004-06-01), Sakurai et al.
patent: 2005/0062523 (2005-03-01), Wang et al.
patent: 2006/0041768 (2006-02-01), Weber et al.
patent: A-5-34419 (1993-02-01), None
patent: A-8-161001 (1996-06-01), None
patent: 10307167 (1998-11-01), None
patent: 11352195 (1999-12-01), None
Dufaza, C., IHS, H, “Test synthesis for DC test and maximal diagnosis of swtiched-capacitor circuits”,□□VLSI Test Symposium, 1997, 15th IEEE, Apr. 27-May 1, 1997 pp. 252-260 □□.
Renovell, M., Azias, F., Bodin, J.C., Bertrand, Y, “Design-for-testability for switched-current circuits”, VLSI Test Symposium, 1998. Proceedings. 16th IEEE, Apr. 26-30, 1998 pp. 370-375 □□.

Affiliated with

Also associated with

Rating

Test mode circuit and reset control method therefor does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Test mode circuit and reset control method therefor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Test mode circuit and reset control method therefor will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4024443