Semiconductor memory device and data write method thereof

Details Semiconductor memory device and data write method thereof Semiconductor memory device and data write method thereof

2006-11-17

2008-12-23

Ho, Hoai V. (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185030

Reexamination Certificate

active

07468914

ABSTRACT:
A semiconductor memory device including a memory cell array and a sense amplifier, wherein the memory cell array includes: a plurality of information cells, in each of which either one of multi-level data is written; a first reference cell with the same structure and the same connection state as the information cell, in which a reference data level is written for generating a first reference current; and a second reference cell, which serves for generating a second reference current used for setting the lowest data level of the multi-level data and for setting the reference data level of the first reference cell.

REFERENCES:
patent: 6807096 (2004-10-01), Toda
patent: 6847555 (2005-01-01), Toda
patent: 7006380 (2006-02-01), Toda
patent: 7283397 (2007-10-01), Harari et al.
patent: 2002/0021581 (2002-02-01), Lin
patent: 2006/0209593 (2006-09-01), Toda
patent: 2006/0239073 (2006-10-01), Toda
patent: 2007/0121376 (2007-05-01), Toda
U.S. Appl. No. 11/476,023, filed Jun. 28, 2006, Haruki Toda.
U.S. Appl. No. 11/832,987, filed Aug. 2, 2007, Toda.

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