Instruction decoder including emulation using indirect specifier

Details Instruction decoder including emulation using indirect specifier Instruction decoder including emulation using indirect specifier

1996-05-16

1998-08-11

Donaghue, Larry D.

395595, 395598, 395568, 395391, G06F 930

Patent

active

057940630

ABSTRACT:
A ROM-based decoder exploits the high degree of redundancy between instructions to share various operation structures and substantially reduce memory size. The decoder includes a circuit which merges and shares common ROM sequences to reduce ROM size. A superscalar microprocessor includes an instruction decoder having an emulation code control circuit and an emulation ROM which emulates the function of a logic instruction decoder. An instruction register is loaded with a current instruction and has various bit-fields that are updated according to the state of the processor. An entry point circuit derives an emulation ROM entry point from the instruction stored in the instruction register. The emulation ROM entry point is used to address the emulation ROM, from which an operation (Op) is read. Various fields in the Op are selectively substituted from the instruction register and emulation environment registers.

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