Integrated semiconductor memory array and method for operating t

Details Integrated semiconductor memory array and method for operating t Integrated semiconductor memory array and method for operating t

1993-06-09

1994-07-12

Fears, Terrell W.

Static information storage and retrieval

Addressing

36518905, 36523005, 36523009, 365239, G11C 1300

Patent

active

053294939

ABSTRACT:
An integrated semiconductor memory array includes a memory region, a writing buffer memory associated with the memory region, a writing pointer and an input buffer associated with the writing buffer memory, a reading buffer memory associated with the memory region, a reading pointer and an output buffer associated with the reading buffer memory, and a control device being formed of a memory control circuit and a data flow control circuit. A reading column address decoder controlling the reading pointer is associated with the reading buffer memory. A reading address control unit is connected to the reading column address decoder, and a reading address register is connected to the reading address control unit. A writing column address decoder controlling the writing pointer is associated with the writing buffer memory. A writing address control unit is connected to the writing column address decoder, and a writing address register is connected to the writing address control unit. A line address decoder is provided in the memory control circuit or in the memory region and is triggerable by the reading address control unit and the writing address control unit.

REFERENCES:
patent: 4855959 (1989-08-01), Kobayashi
patent: 4858190 (1989-08-01), Yamaguchi
patent: 4882710 (1989-11-01), Hashimoto et al.
patent: 5093807 (1992-03-01), Hashimoto et al.
patent: 5214609 (1993-05-01), Kato et al.

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