Staggered wirebonding configuration

Details Staggered wirebonding configuration Staggered wirebonding configuration

2005-11-03

2008-08-12

Menz, Douglas M (Department: 2891)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With contact or lead

C257S786000, C257S723000

Reexamination Certificate

active

07411287

ABSTRACT:
The present invention discloses a staggered finger configuration comprising a plurality of first and second conducting wires alternately arranged on the substrate, wherein each of the first conducting wire connecting an inner and an outer fingers and each of the second conducting wire connecting an intermediate finger between the inner and the outer fingers, thereby forming a staggered configuration.

REFERENCES:
patent: 5420460 (1995-05-01), Massingill
patent: 5592020 (1997-01-01), Nakao et al.
patent: 6008532 (1999-12-01), Carichner
patent: 6538336 (2003-03-01), Secker et al.
patent: 6603199 (2003-08-01), Poddar
patent: 6714421 (2004-03-01), Chen et al.
patent: 2006/0091558 (2006-05-01), Huang et al.
patent: 2006/0267175 (2006-11-01), Lee

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