Oscillators – Combined with particular output coupling network
Reexamination Certificate
2006-10-17
2008-08-26
Mis, David (Department: 2817)
Oscillators
Combined with particular output coupling network
C331S00100A, C331S016000, C331S044000, C331S176000, C327S117000, C327S156000
Reexamination Certificate
active
07417510
ABSTRACT:
A clock synthesis circuit includes a delta sigma modulator that receives a divide ratio and generates an integer portion and a digital quantization error (a fractional portion). A fractional-N divider divides a received signal according to a divide control value corresponding to the integer portion and generates a divided signal. A phase interpolator adjusts a phase of the divided signal according to the digital quantization error to thereby reduce noise associated with the fractional-N divider.
REFERENCES:
patent: 7181180 (2007-02-01), Teo et al.
Allen, Daniel J. and Carley, Adam L., “Free-Running Ring Frequency Synthesizer,” 2006 IEEE International Solid-State Circuits Conference, Feb. 7, 2006, pp. 380-381.
Dai, Fa Foster et al., “A Direct Digital Frequency Synthesizer with Fourth-Order Phase Domain ΔΣ Noise Shaper and 12-bit Current-Steering DAC,” IEEE Journal of Solid-State Circuits, vol. 41, No. 4, Apr. 2006, pp. 839-850.
Meninger, Scott E. and Perrott, Michael H., “A 1-MHZ Bandwidth 3.6GHz 0.18-μm CMOS Fractional-N Synthesizer Utilizing a Hybrid PFD/DAC Structure for Reduced Broadband Phase Noise,” IEEE Journal of Solid-State Circuits, vol. 41, No. 4, Apr. 2006, pp. 966-980.
Yang, Chin-Yuan et al., “A High-Frequency Phase-Compensation Fractional-N Frequency Synthesizer,” IEEE International Symposium on Circuits and Systems, 2005 ISCAS, May 23-26, 2005, pp. 5091-5094.
Mis David
Silicon Laboratories Inc.
Zagorin O'Brien Graham LLP
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