Information processing device with improved timing of clock and

Details Information processing device with improved timing of clock and Information processing device with improved timing of clock and

1996-11-19

1998-08-11

Heckler, Thomas M.

39575004, G06F 104, G06F 130

Patent

active

057940223

ABSTRACT:
An information processing device with improved timing of clock and reset signals, wherein at a rise time of a power supply voltage, when a clock signal generated by a buffer gate based on a sinusoidal wave reference signal output from an oscillation circuit is detected by a monitor circuit, a reset release signal is supplied from a reset circuit to a microcomputer after a predetermined time lapse specified by a delay circuit consisting of OR gates and a series of F/Fs while, at a fall time of the power supply voltage, when a similar state to a previous state when the clock signal has been terminated is detected by the monitor circuit, the clock signal is terminated after a reset signal is supplied to the microcomputer.

REFERENCES:
patent: 4642757 (1987-02-01), Sakamoto
patent: 4653018 (1987-03-01), Stadlmeier et al.
patent: 5179693 (1993-01-01), Kitamura et al.
patent: 5511203 (1996-04-01), Wisor et al.

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