Phase locked loop for stably operating in a matter that is...

Details Phase locked loop for stably operating in a matter that is... Phase locked loop for stably operating in a matter that is...

2006-07-14

2008-10-28

Pascal, Robert J. (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Particular error voltage control

C331S016000, C327S157000

Reexamination Certificate

active

07443249

ABSTRACT:
A phase locked loop for stably operating in a matter that is insensitive to variation in PVT and a method of operating the same. The PLL according to the present invention includes a PFD, a charge pump circuit, a loop filter, a VCO, and a peak voltage detector. The PFD compares a phase or frequency of a reference signal with a phase or frequency of an output signal and outputs an up signal or a down signal based on the comparison result. The charge pump circuit generates a pumping current in response to the up signal or the down signal and increases or decreases the pumping current in response to a detection signal. The loop filter outputs control voltage according to the pumping current. The VCO outputs the output signal having a frequency determined based on the control voltage. The peak voltage detector detects the peak value of the control voltage and outputs the detection signal based on the detection result. The PLL detects the peak value of control voltage and controls the operation of a charge pump circuit based on the detection result thereby decreasing the peaking and ringing phenomena of the control voltage and then stably operating in a manner that is insensitive to variation in PVT.

REFERENCES:
patent: 6043695 (2000-03-01), O'Sullivan
patent: 6717475 (2004-04-01), McCarthy
patent: 6724265 (2004-04-01), Humphreys
patent: 6998922 (2006-02-01), Jensen et al.
patent: 09-130241 (1997-05-01), None
patent: 10-200406 (1998-07-01), None

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