Electrical computers and digital processing systems: processing – Instruction issuing
Reexamination Certificate
2004-06-30
2008-10-14
Chan, Eddie P (Department: 2183)
Electrical computers and digital processing systems: processing
Instruction issuing
Reexamination Certificate
active
07437538
ABSTRACT:
An apparatus and method for floating-point special case handling. In one embodiment, a processor may include a first execution unit configured to execute a longer-latency floating-point instruction, and a second execution unit configured to execute a shorter-latency floating-point instruction. In response to the longer-latency floating-point instruction being issued to the first execution unit, the second execution unit may be further configured to detect whether a result of the longer-latency floating-point instruction is determinable from one or more operands of the longer-latency floating-point instruction independently of the first execution unit executing the longer-latency floating-point instruction. In response to detecting that the result is determinable, the second execution unit may be further configured to flush the longer-latency floating-point instruction from the first execution unit and to determine the result.
REFERENCES:
patent: 4845659 (1989-07-01), Hrusecky
patent: 4879676 (1989-11-01), Hansen
patent: 5046068 (1991-09-01), Kubo et al.
patent: 5193158 (1993-03-01), Kinney et al.
patent: 5257215 (1993-10-01), Poon
patent: 5339266 (1994-08-01), Hinds et al.
patent: 5386375 (1995-01-01), Smith
patent: 5488729 (1996-01-01), Vegesna et al.
patent: 5515308 (1996-05-01), Karp et al.
patent: 5546593 (1996-08-01), Kimura et al.
patent: 5548545 (1996-08-01), Brashears et al.
patent: 5559977 (1996-09-01), Avnon et al.
patent: 5619439 (1997-04-01), Yu et al.
patent: 5812439 (1998-09-01), Hansen
patent: 5867724 (1999-02-01), McMahon
patent: 5954789 (1999-09-01), Yu et al.
patent: 6076157 (2000-06-01), Borkenhagen et al.
patent: 6088788 (2000-07-01), Borkenhagen et al.
patent: 6088800 (2000-07-01), Jones et al.
patent: 6105127 (2000-08-01), Kimura et al.
patent: 6131104 (2000-10-01), Oberman
patent: 6212544 (2001-04-01), Borkenhagen et al.
patent: 6219778 (2001-04-01), Panwar et al.
patent: 6243788 (2001-06-01), Franke et al.
patent: 6282554 (2001-08-01), Abdallah et al.
patent: 6317840 (2001-11-01), Dean et al.
patent: 6341347 (2002-01-01), Joy et al.
patent: 6349319 (2002-02-01), Shankar et al.
patent: 6357016 (2002-03-01), Rodgers et al.
patent: 6397239 (2002-05-01), Oberman et al.
patent: 6415308 (2002-07-01), Dhablania
patent: 6427196 (2002-07-01), Adiletta et al.
patent: 6434699 (2002-08-01), Jones et al.
patent: 6460134 (2002-10-01), Blomgren et al.
patent: 6470443 (2002-10-01), Emer et al.
patent: 6496925 (2002-12-01), Rodgers et al.
patent: 6507862 (2003-01-01), Joy et al.
patent: 6523050 (2003-02-01), Dhablania et al.
patent: 6564328 (2003-05-01), Grochowski et al.
patent: 6567839 (2003-05-01), Borkenhagen et al.
patent: 6594681 (2003-07-01), Prabhu
patent: 6625654 (2003-09-01), Wolrich et al.
patent: 6629236 (2003-09-01), Aipperspach et al.
patent: 6629237 (2003-09-01), Wolrich et al.
patent: 6631392 (2003-10-01), Jiang et al.
patent: 6633895 (2003-10-01), Bass et al.
patent: 6651158 (2003-11-01), Burns et al.
patent: 6668308 (2003-12-01), Barroso et al.
patent: 6668317 (2003-12-01), Bernstein et al.
patent: 6671827 (2003-12-01), Guilford et al.
patent: 6681345 (2004-01-01), Storino et al.
patent: 6687838 (2004-02-01), Orenstien et al.
patent: 6694347 (2004-02-01), Joy et al.
patent: 6694425 (2004-02-01), Eickemeyer
patent: 6697935 (2004-02-01), Borkenhagen et al.
patent: 6728845 (2004-04-01), Adiletta et al.
patent: 6748556 (2004-06-01), Storino et al.
patent: 6801997 (2004-10-01), Joy et al.
patent: 6820107 (2004-11-01), Kawai et al.
patent: 6847985 (2005-01-01), Gupta et al.
patent: 6857064 (2005-02-01), Smith et al.
patent: 6883107 (2005-04-01), Rodgers et al.
patent: 6889319 (2005-05-01), Rodgers et al.
patent: 6898694 (2005-05-01), Kottapalli et al.
patent: 7143412 (2006-11-01), Koenen
patent: 2002/0156999 (2002-10-01), Eickemeyer et al.
patent: 2003/0028759 (2003-02-01), Prabhu et al.
patent: 2004/0059769 (2004-03-01), Cornea-Hasegan
Standards Committee of the IEEE Computer Society, “An American National Standard IEEE Standard for Binary Floating-Point Arithmetic”, 1985, IEEE.
Kalla et al., IBM Power5 Chip: A Dual-Core Multithreaded Processor, IEEE MICRO, vol. 24, No. 2, Apr. 2004, pp. 40-47.
Sun Microsystems,“MAJC Architecture Tutorial. White Paper,” Sep. 1999, pp. 1-31.
Sun Microsysems, “Introduction to Throughput Computing,” Feb. 2003, pp. 1-18.
Kongetira, et al., “Niagara: A 32-Way Multithreaded Sparc Processor,” IEEE Micro, vol. 25, No. 2, Apr. 2005, pp. 21-29.
U.S. Appl. No. 10/880,713, filed Jun. 30, 2004.
U.S. Appl. No. 10/880,488, filed Jun. 30, 2004.
Tulsen et al., “Power-sensitive multithreaded architecture,” IEEE 2000, pp. 199-206.
Uhrig et al., “Hardware-based power management for real-time applications,” Proceedings of the Second International Symposium on Parallel and Distributed Computing, IEEE 2003, 8 pages.
Tullsen, et al., “Simultaneous Multithreading: Maximizing On-Chip Parallelism,” ISCA 1995, pp. 533-544.
Tullsen, et al., “Exploiting Choice: Instruction Fetch and Isssue on an Implementable Simultaneous Multithreading Processor,” pp. 191-202, 1996.
Smith, “The End of Architecture,” May 29, 1990, pp. 10-17.
Alverson et al., “Tera Hardware-Software Cooperation,” 16 pages, 1997.
Ungerer et al., “A Survey of Processors with Explicit Multithreading,” ACM Computing Surveys, vol. 35, No. 1, Mar. 2003, pp. 29-63.
Alverson et al., “The Tera Computer System,” ACM 1990, 6 pages.
Alverson et al., “Exploiting Heterogenous Parallelism on a Multithreaded Multiprocessor,” ACM 1992, pp. 188-197.
Uhrig, et al., “Implementing Real-Time Scheduling Within A Multithreaded Java Microcontroller,” 8 pages. 2002.
Ide, et al., “A 320-MFLOPS CMOS Floating-Point Processing Unit for Superscalar Processors,” IEEE 1993, 5 pages.
Nemawarkar, et al., “Latency Tolerance: A Metric for Performance Analysis of Multithreaded Architectures,” IEEE 1997, pp. 227-232.
Baniasadi, et al., “Instruction Flow-Based Front-end Throttling for Power-Aware High-Performance Processors,” ACM 2001, pp. 16-21.
Gura, et al., “An End-to-End Systems Approach to Elliptic Curve Cryptography,” 16 pages. 2002.
Eberle, et al., “Cryptographic Processor for Arbitrary Elliptic Curves over GF(2m),” 11 pages. 2003.
Brooks Jeffrey S.
Olson Christopher H.
Chan Eddie P
Kowert Robert C.
Lindlof John
Meyertons Hood Kivlin Kowert & Goetzel P.C.
Petro Anthony M.
LandOfFree
Apparatus and method for reducing execution latency of... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Apparatus and method for reducing execution latency of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus and method for reducing execution latency of... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4005926