Method for reading a single-poly single-transistor...

Details Method for reading a single-poly single-transistor... Method for reading a single-poly single-transistor...

2007-01-23

2008-08-26

Tran, Andrew Q (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185270

Reexamination Certificate

active

07417897

ABSTRACT:
A method for operating a single-poly, single-transistor (1-T) non-volatile memory (NVM) cell. The NVM cell includes a gate on a P substrate, a gate dielectric layer, an N drain region and an N source region. N channel is defined between the N drain region and N source region. The NVM cell is programmed by breaking down the gate dielectric layer. To read the NVM cell, a positive voltage is provided to N drain region, a positive voltage is provided to the gate, and grounding the N source region and the P substrate.

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J.Peng, et al., “A Novel Embedded OTP NVM using Standard Foundry CMOS Logic Technology”, Bernard Aronson, Kilopass, USA, p. 24, IEEE Non-Volatile Semiconductor Memory Workshop, 2006.

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