Patent
1995-05-30
1997-06-03
Teska, Kevin J.
G06F 1312
Patent
active
056363702
ABSTRACT:
A conversion cache circuit, interfacing RISC busses to CISC peripheral circuits, provides master/slave Write and Read operations in a shared memory (130) and in the internal registers of the processor of said peripheral circuits (210). It enables RISC processor to Write and Read in the internal registers of the 8-bit processor in a salve operation while the 32-bit processor may perform the Write or Read operations to the shared memory through the conversion cache circuit in a master mode. The 32-bit processor may have access directly to the memory through its own direct access memory mechanism.
REFERENCES:
patent: 4057846 (1977-11-01), Cockerill et al.
patent: 5193167 (1993-03-01), Sites et al.
patent: 5333259 (1994-07-01), Jung
patent: 5371860 (1994-12-01), Mura et al.
patent: 5388242 (1995-02-01), Jewett
patent: 5457780 (1995-10-01), Shaw et al.
patent: 5530822 (1996-06-01), Beavers et al.
patent: 5560029 (1996-09-01), Papadopoulos et al.
IBM Technical Disclosure Bulletin, vol. 26, No. 3B, Aug. 1983, pp. 1507-1511.
Benayoun Alain
LePennec Jean-Francois
Michel Patrick
Sicsic Patrick
Cockburn Joscelyn G.
Fiul Dan
International Business Machines - Corporation
Teska Kevin J.
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