Electrical computers and digital processing systems: processing – Processing architecture – Microprocessor or multichip or multimodule processor having...
Reexamination Certificate
2004-02-27
2008-10-21
Chan, Eddie P (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Microprocessor or multichip or multimodule processor having...
C712S010000, C712S016000
Reexamination Certificate
active
07441100
ABSTRACT:
A method for synchronizing a plurality of processors of a multi-processor computer system on a synchronization point is disclosed. The method includes triggering a first set of processors, using a lead processor of the plurality of processors when the lead processor encounters the synchronization point, to enter an exit holding loop. The first set of processors representing the plurality of processors except the lead processor. The triggering the first set of processors is performed without accessing a shared memory area of the multi-processor system. There is also included triggering the plurality of processors, using a tail processor of the plurality of processors when the tail processor encounters the synchronization point, to leave the exit holding loop. The triggering the plurality of processors is performed without accessing the shared memory area of the multi-processor system.
REFERENCES:
patent: 5434995 (1995-07-01), Oberlin et al.
patent: 5887167 (1999-03-01), Sutton
patent: 6735760 (2004-05-01), Dice
Johnson et al.; Cyclical Cascade Chains: A Dynamic Barrier Synchronization Mechanism for Multiprocessor Systems; 2001; IEEE; pp. 1-8.
Chen Chenghung Justin
Curry John W.
Seymour Robert
Chan Eddie P
Faherty Corey S
Hewlett--Packard Development Company, L.P.
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