Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2005-08-24
2008-09-02
Luu, Pho M. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular connection
C365S185260, C365S185270
Reexamination Certificate
active
07420842
ABSTRACT:
A storage transistor is programmed as a non-volatile memory element by biasing the source and drain while a programming voltage is applied to the gate. The substrate is held at a different potential than the source/drain to insure that the greatest difference in voltage during the programming step occurs between the channel region and the gate, rather than the gate and the source/drain. The programming voltage heats the channel region to form a non-volatile low-resistance connection between the source and drain, which is read to determine the programmed state.
REFERENCES:
patent: 5371395 (1994-12-01), Hawkins
patent: 5646903 (1997-07-01), Johnson
patent: 5737261 (1998-04-01), Taira
patent: 5796650 (1998-08-01), Wik et al.
patent: 5808932 (1998-09-01), Irrinki et al.
patent: 5822267 (1998-10-01), Watanabe et al.
patent: 5946575 (1999-08-01), Yamaoka et al.
patent: 6156593 (2000-12-01), Peng et al.
patent: 6266269 (2001-07-01), Karp et al.
patent: 6510085 (2003-01-01), Fastow et al.
patent: 6521946 (2003-02-01), Mosher
patent: 2002/0074606 (2002-06-01), Mosher
patent: 2003/0071316 (2003-04-01), Gonzalez et al.
patent: 2003/0127681 (2003-07-01), Nishioka et al.
patent: 2003/0173638 (2003-09-01), Hayashi
patent: 2003/0178683 (2003-09-01), Hayashi
patent: 2004/0223363 (2004-11-01), Peng
patent: 2006/0292754 (2006-12-01), Min et al.
U.S. Appl. No. 11/210,496, filed Aug. 24, 2005, Karp et al.
U.S. Appl. No. 11/210,499, filed Aug. 24, 2005, Toutounchi et al.
U.S. Appl. No. 11/210,500, filed Aug. 24, 2005, Karp et al.
Iranmanesh, Ali et al., “Antifuse Reliability and Link Formation Models”, 1994 Int'l Integrated Reliability Workshop Final Report, Oct. 16-19, 1994, pp. 90-94, available from IEEE, 3 Park Avenue, 17th Floor, New York, NY 10016-5997.
Ahrens Michael G.
Jeong Jongheon
Karp James
Toutounchi Shahin
Hardaway Michael R.
Hewett Scott
Luu Pho M.
Xilinx , Inc.
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