Cryptographic device employing parallel processing

Details Cryptographic device employing parallel processing Cryptographic device employing parallel processing

2003-06-13

2008-09-30

Parthasarathy, Pramila (Department: 2136)

Cryptography

Key management

Having particular key generator

C708S706000, C708S708000

Reexamination Certificate

active

07430293

ABSTRACT:
A cryptography processor includes a central processing unit and a co-processor, the co-processor comprising a plurality of calculating subunits as well as a single control unit which is coupled to each of the plurality of calculating subunits. A cryptographic operation is distributed among the individual calculating subunits in the form of sub-operations by the control unit. The central processing unit, the plurality of calculating subunits and the control unit are integrated on a single chip, the chip comprising a common supply current access for supplying the plurality of calculating subunits and the control unit with current. Due to the arrangement of the calculating subunit in parallel, on the hand, the throughput of the cryptography processor is increased. On the other hand, however, the current profile that may be detected at the supply current access is randomised to such an extent that an attacker can no longer infer numbers processed in the individual calculating subunits.

REFERENCES:
patent: 4870681 (1989-09-01), Sedlak
patent: 6408075 (2002-06-01), Ohki et al.
patent: 6735611 (2004-05-01), Vanstone
patent: 36 31 992 (1987-11-01), None
patent: 195 39 700 (1996-11-01), None
patent: 2 787 900 (2000-06-01), None
patent: 2 789 535 (2000-08-01), None
patent: 2 130 405 (1984-05-01), None
Walter, C. D.: “Improved Linear Systolic Array for Fast Modular Exponentiation”, IEE Proc.-Comput. Digit. Tech., vol. 147, No. 5, Sep. 2000, pp. 323-328.
Groβschädl, J.: “High-Speed RSA Hardware Based on Barret's Modular Reduction Method”, Eds.: C. K. Koc and C. Paar, CHES 2000, LNCS 1965, pp. 191-203, Springer-Verlag, 2000.
Kato, T. et al.: “A Design for Modular Exponentiation Coprocessor in Mobile Telecommunication Terminals”, Eds.: C. K. Koc and C. Paar, CHES 2000, LNCS 1965, pp. 191-203, Springer-Verlag, 2000, 13 pages.
Erwin Hess et al.: “Implementations of cryptographic Algorithms and Countermeasures”,Eurosmart Security Conference Proceedings, Jul. 13-15, 2000, pp. 54-64.
Erwin Hess et al.: “Design of Long Integer Arithmetic Units for Public-Key Algorithms”,Eurosmart Security Conference Proceedings, Jul. 13-15, 2000, pp. 324-334.
David Naccache et al.: “Arithmetic Co-processors for Public-key Cryptography: The State of the Art”,Proc. Of CARDIS '96, Amsterdam, The Netherlands, Sep. 16-18, 1996, pp. 39-58.
Advanced Micro Devices. The AM2900 Family Data Book with Related Support Circuits, Advance micro Devices, Inc., Sunnyvale, CA, USA, 1979, http://www.bitsavers.org/pdf/amd/—dataBooks/1979—AMD—2900family.pdf.
Linley Gwennap:“UltraSparc Adds Multimedia Instructions”, Dec. 5, 1994.

Affiliated with

Also associated with

Rating

Cryptographic device employing parallel processing does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Cryptographic device employing parallel processing, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Cryptographic device employing parallel processing will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3988740