Phase synchronous circuit

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing

Reexamination Certificate

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Details

C327S152000

Reexamination Certificate

active

07423461

ABSTRACT:
An external clock round-trips a round-trip delay block configured by a selector and a short delay array, and is made capable of corresponding to a wide frequency by generating a long delay time required for synchronization at the time of a low frequency operation. Further, when a plurality of phase comparators are disposed, in both cases where comparing phases all at once and comparing phases one after another, it is possible to complete the phase synchronization within a short time by making a delay amount variable.

REFERENCES:
patent: 6292040 (2001-09-01), Iwamoto et al.
patent: 6396322 (2002-05-01), Kim et al.
patent: 6919745 (2005-07-01), Lee et al.
patent: 6933758 (2005-08-01), Kim et al.
patent: 7157951 (2007-01-01), Morrison et al.
patent: 7253670 (2007-08-01), Sasaki
patent: 7259601 (2007-08-01), Zarate et al.
patent: 2005/0146365 (2005-07-01), Kim et al.
patent: 2000-194438 (2000-07-01), None
patent: 2001-197047 (2001-07-01), None
patent: 2003-69424 (2003-03-01), None
Takanori Saeki et al. , “A 2.5-ns Clock Access, 250-MHz, 256-Mb SDRAM with Synchronous Mirror Delay” IEEE Journal of Solid-state Circuits, vol. 31, No. 11, Nov. 1996, pp. 1656-1668.

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