Method for forming stacked via-holes in a multilayer printed...

Details Method for forming stacked via-holes in a multilayer printed... Method for forming stacked via-holes in a multilayer printed...

2006-11-16

2008-09-02

Arbes, C. J (Department: 3729)

Metal working

Method of mechanical manufacture

Electrical device making

C029S825000, C029S830000, C029S846000, C219S121710, C427S097100

Reexamination Certificate

active

07418780

ABSTRACT:
An exemplary method for forming stacked via-holes in a multilayer printed circuit board includes the steps of: providing a base circuit board; attaching a first copper-coated-substrate having a first substrate and a first copper layer thereon and a second copper-coated-substrate having a second substrate and a second copper layer thereon onto the base circuit board in a manner such that; forming at least one first window in the second copper layer, making at least one first hole in the second substrate through the at least one first window, forming at least one second window in the first copper layer through the at least one first hole, and making at least one second hole in the first substrate through the at least one second window, thus forming at least one part-finished stacked via-hole; and plating the at least one part-finished stacked via-hole thereby forming at least one stacked via-hole.

REFERENCES:
patent: 5826330 (1998-10-01), Isoda et al.
patent: 6021564 (2000-02-01), Hanson
patent: 6023041 (2000-02-01), Noddin
patent: 6103992 (2000-08-01), Noddin
patent: 6132853 (2000-10-01), Noddin
patent: 6203891 (2001-03-01), Noddin
patent: 6407363 (2002-06-01), Dunsky et al.
patent: 2005/0099785 (2005-05-01), Chang

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