Monolithic, combo nonvolatile memory allowing byte, page and...

Details Monolithic, combo nonvolatile memory allowing byte, page and... Monolithic, combo nonvolatile memory allowing byte, page and...

Filed on

2006-03-28

Date issued

2008-05-13

Examiner

Zarabian, Amir (Department: 2827)

Patent Class

Static information storage and retrieval

SubClass

Floating gate

SubSubClass

Particular biasing

Other Related Categories

C365S185050, C365S185110, C365S185270, C257S340000, C257S797000

Type

Reexamination Certificate

Status

active

Patent number

07372736

Description

ABSTRACT:
A nonvolatile memory array has a single transistor flash memory cell and a two transistor EEPROM memory cell which maybe integrated on the same substrate. The nonvolatile memory cell has a floating gate with a low coupling coefficient to permit a smaller memory cell. The floating gate placed over a tunneling insulation layer, the floating gate is aligned with edges of the source region and the drain region and having a width defined by a width of the edges of the source the drain. The floating gate and control gate have a relatively small coupling ratio of less than 50% to allow scaling of the nonvolatile memory cells. The nonvolatile memory cells are programmed with channel hot electron programming and erased with Fowler Nordheim tunneling at relatively high voltages.

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