Memory device distributed controller system

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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C365S185170

Reexamination Certificate

active

07420849

ABSTRACT:
A memory device distributed controller circuit distributes memory control functions amongst a plurality of memory controllers. A master controller receives an interpreted command and activates the appropriate slave controllers depending on the command. The slave controllers can include a data cache controller that is coupled to and controls the data cache and an analog controller that is coupled to and controls the analog voltage generation circuit. The respective controllers have appropriate software/firmware instructions that determine the response the respective controllers take in response to the received command.

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