Image analysis – Image compression or coding – Interframe coding
Patent
1994-12-22
1997-06-03
Boudreau, Leo
Image analysis
Image compression or coding
Interframe coding
382251, G06K 900
Patent
active
056362935
ABSTRACT:
A circuit implementation of a block matching algorithm includes a plurality of modules. Each module is a one-dimensional systolic array. The modules can be connected in tandem to increase the power of computation so that the best match of a current block in a search window can be obtained more rapidly without increasing the number of input ports. Further, the modules can be connected in tandem so as to enable the size of the search window to be increased.
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L. De Vos et al, "VLSI Architectures for th Full-Search Blockmatching Algorithm", IEEE ICASSP, pp. 1687-1690 (1989).
T. Komarek et al, "Array Architecture for Block Matching Algorithms", IEEE, Trans. on Circ. and Systesm, vol. 36, No. 10, Oct. 1989, pp. 1301-1308.
L. De Vos et al, "Parameterizable VLSI Architecture . . . Algorithm", IEEE Trans. on Cir. and Systems, vol. 36, No. 10, Oct. 1989 pp. 1309-1316.
Kun-Min Yang et al, "A Family of VLSI Designs for the Motion Compensation . . . " IEEE Trans. on Cir. and Systems, vol. 36, No. 10, Oct. 1989, pp. 1317-1325.
Lee Foo-Ming
Lin Vincent M. S.
Boudreau Leo
Industrial Technology Research Institute
Tadayon Bijan
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