Modified-layer EPROM cell

Static information storage and retrieval – Floating gate – Particular connection

Reexamination Certificate

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C365S185260

Reexamination Certificate

active

07345915

ABSTRACT:
An EPROM cell includes a semiconductor substrate, having source and drain regions, a floating gate, including a semiconductive polysilicon layer electrically interconnected with a first metal layer, and a control gate, including a second metal layer. The floating gate is disposed adjacent to the source and drain regions and separated from the semiconductor substrate by a first dielectric layer, and the second metal layer of the control gate is capacitively coupled to the first metal layer with a second dielectric layer therebetween.

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