Floating point square root provider with embedded status...

Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed

Reexamination Certificate

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C708S525000

Reexamination Certificate

active

07430576

ABSTRACT:
A system for providing a floating point square root comprises an analyzer circuit configured to determine a first status of a first floating point operand based upon data within the first floating point operand. In addition, the system comprises a results circuit coupled to the analyzer circuit. The results circuit is configured to assert a resulting floating point operand containing the square root of the first floating point operand and a resulting status embedded within the resulting floating point operand.

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Title: Lecture Notes on the Status of “IEEE Standard 754 for Binary Floating-Point Arithmetic”, by Prof. W. Kahan, May 31, 1996, pp. 1-30.
Title: “Interval Arithmetic Specification” by Dmitri Chiriaev & G. William Walster, Draft revised May 4, 1998, pp. 1-78.
Title: “IEEE Standard for Binary Floating-Point Arithmetic IEEE Standard 754-1985,” by Standards Committee of the IEEE Computer Society, The Institute of Electrical and Electronics Engineers, Inc., copyright 1985, pp. 1-14.

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