Method and device for calculating an iterated state for a...

Details Method and device for calculating an iterated state for a... Method and device for calculating an iterated state for a...

2004-10-12

2008-09-16

Ngo, Chuong D (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

Reexamination Certificate

active

07426528

ABSTRACT:
A final state in a shift register arrangement is obtained from an initial state by means of N-fold iteration using an iteration rule prescribed by a characteristic polynomial f(x) of n-th order. To determine the final state, a tap mask which is characteristic of N′ shift register operations is calculated. Using the tap mask, n shift register operations are performed. This produces the n bits of an N′-fold iterated state of the shift register arrangement. Any remaining N-N′ iterations which are needed are performed in another manner.

REFERENCES:
patent: 5926070 (1999-07-01), Barron et al.
patent: 6005888 (1999-12-01), Barron
patent: 6038577 (2000-03-01), Burshtein
patent: 6173009 (2001-01-01), Gu
patent: 6339781 (2002-01-01), Sasaki
patent: 6647054 (2003-11-01), Greenhoe
patent: 196 35 110 (1997-04-01), None
patent: 693 26 681 (2000-02-01), None
patent: WO 03/028239 (2003-04-01), None
“Universal Mobile Telecommunications system (UMTS); Spreading and Modulation (FDD) (#GPP TS 25.213 version 4.2.0 Release 4)” pp. 1-27.

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