Semiconductor memory device with MOS transistors each having...

Details Semiconductor memory device with MOS transistors each having... Semiconductor memory device with MOS transistors each having...

2006-10-02

2008-09-23

Pham, Ly D (Department: 2827)

Static information storage and retrieval

Interconnection arrangements

C365S185050, C365S185110, C365S072000, C365S230030

Reexamination Certificate

active

07428161

ABSTRACT:
A semiconductor memory device includes memory cell arrays, word lines, bit lines, column gates, sense amplifiers, and an error correcting circuit. The memory cell array includes first regions and a second region. The first region includes first element isolating regions which have stripe shapes along the bit lines. The memory cell is formed on an element region between the adjacent element isolating regions. The first regions are arranged in plurality along the word line direction. The second region is provided adjacent to the first region in a direction along the word lines. The second region includes a second element isolating region whose width along the word line direction is greater than that of the first element isolating region. Addresses of the bit line adjacent to the second region are different from one another among the memory cell arrays.

REFERENCES:
patent: 5142541 (1992-08-01), Kim et al.
patent: 2003/0193827 (2003-10-01), Choi
patent: 2004/0197990 (2004-10-01), Hieda
patent: 2-166700 (1990-06-01), None
Wei-Hua Liu, et al., “A 2-Transistor Source-Select (2TS) Flash EEPROM for 1.8V-Only Applications”, Non-Volatile Semiconductor Memory Workshop (NVSMW), 4.1, Feb. 1997, pp. 1-3.

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