System and method to synchronize signals in individual...

Details System and method to synchronize signals in individual... System and method to synchronize signals in individual...

2006-04-21

2008-07-29

Elms, Richard T. (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S194000, C327S158000

Reexamination Certificate

active

07405996

ABSTRACT:
A synchronous output signal generated by an integrated circuit (IC) component is synchronized to an applied clock signal for each individual IC component. A variable feedback delay in the IC component is incrementally altered to alter the phase skew between the clock signal and the output signal. The relative phase order of the clock and output signals is monitored in the IC component. In response to detecting a swap in the relative phase order of the clock and output signals, the variable feedback delay ceases to be altered. In some embodiments, the IC component may be a SDRAM component.

REFERENCES:
patent: 7277357 (2007-10-01), Ma
patent: 2006/0255846 (2006-11-01), Drexler et al.
patent: 2007/0086267 (2007-04-01), Kwak

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