Non-volatile semiconductor memory device and writing method...

Details Non-volatile semiconductor memory device and writing method... Non-volatile semiconductor memory device and writing method...

2005-06-08

2008-03-04

Hur, J. H. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185050, C365S185230, C365S233100, C365S194000, C365S185140

Reexamination Certificate

active

07339827

ABSTRACT:
In connection with rise and fall of a word line bias, the present invention adopts a procedure such that a diffusion region voltage Vs on a memory transistor side is changed, and after the voltage Vs passes a certain intermediate value Vsx, a gate voltage Vmg of the memory transistor is changed. Alternatively, there is adopted a procedure such that the gate voltage Vmg of the memory transistor is changed, and after the voltage Vmg passes a certain intermediate value Vmgx, the diffusion layer voltage Vs on the memory transistor side is changed. The values of Vsx and Vmgx are determined from the magnitude of the electric field in a gate insulating film not causing FN tunneling electron injection that causes a change in threshold voltage and the magnitude of a potential barrier against holes not causing BTBT hot hole injection.

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A JPO computer translation of JP 07030076 A.
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