Electrical computers and digital processing systems: multicomput – Multicomputer data transferring via shared memory – Partitioned shared memory
Reexamination Certificate
2008-01-15
2008-01-15
Harrell, Robert B (Department: 2142)
Electrical computers and digital processing systems: multicomput
Multicomputer data transferring via shared memory
Partitioned shared memory
Reexamination Certificate
active
10202753
ABSTRACT:
A packet processing system may include a processor, a cache, a memory controller, and at least one packet interface circuit integrated into a single integrated circuit. In one embodiment (which may be used in integrated or non-integrated systems), the packet interface circuit is configured to cause allocation in the cache of a portion of a received packet. In one embodiment (which may be used in integrated or non-integrated systems), the memory controller may be configured to selectively block memory transactions. Particularly, the memory controller may implement at least two block signals, one for the packet interface circuit and one for other devices. The block signals may be used to control the initiation of memory transactions when the memory controller's input queue is approaching fullness.
REFERENCES:
patent: 4433378 (1984-02-01), Leger
patent: 4463424 (1984-07-01), Mattson et al.
patent: 4760571 (1988-07-01), Schwarz
patent: 5640399 (1997-06-01), Rostoker et al.
patent: 5668809 (1997-09-01), Rostoker et al.
patent: 5778414 (1998-07-01), Winter et al.
patent: 5802287 (1998-09-01), Rostoker et al.
patent: 5805854 (1998-09-01), Shigeeda
patent: 5829025 (1998-10-01), Mittal
patent: 5887187 (1999-03-01), Rostoker et al.
patent: 5889969 (1999-03-01), Getzlaff et al.
patent: 5893150 (1999-04-01), Hagersten et al.
patent: 5893155 (1999-04-01), Cheriton
patent: 5908468 (1999-06-01), Hartmann
patent: 5914955 (1999-06-01), Rostoker et al.
patent: 5974508 (1999-10-01), Maheshwari
patent: 6018763 (2000-01-01), Hughes et al.
patent: 6021451 (2000-02-01), Bell et al.
patent: 6026461 (2000-02-01), Baxter et al.
patent: 6092137 (2000-07-01), Huang et al.
patent: 6098064 (2000-08-01), Pirolli et al.
patent: 6111859 (2000-08-01), Godfrey et al.
patent: 6151662 (2000-11-01), Christie
patent: 6157623 (2000-12-01), Kerstein
patent: 6202125 (2001-03-01), Patterson et al.
patent: 6202129 (2001-03-01), Palanca et al.
patent: 6209020 (2001-03-01), Angle et al.
patent: 6215497 (2001-04-01), Leung
patent: 6262594 (2001-07-01), Cheung et al.
patent: 6266797 (2001-07-01), Godfrey et al.
patent: 6269427 (2001-07-01), Kuttanna et al.
patent: 6279087 (2001-08-01), Melo et al.
patent: 6321309 (2001-11-01), Bell et al.
patent: 6332179 (2001-12-01), Okpisz et al.
patent: 6349365 (2002-02-01), McBride
patent: 6366583 (2002-04-01), Rowett et al.
patent: 6373846 (2002-04-01), Daniel et al.
patent: 6393487 (2002-05-01), Boucher et al.
patent: 6425060 (2002-07-01), Mounes-Toussi et al.
patent: 6438651 (2002-08-01), Slane
patent: 6574708 (2003-06-01), Hayter et al.
patent: 6668308 (2003-12-01), Barroso et al.
patent: 6751704 (2004-06-01), Ng
patent: 0 498 201 (1992-08-01), None
patent: 0 748 087 (1996-12-01), None
patent: 00/30322 (2000-05-01), None
patent: WO 00/30322 (2000-05-01), None
patent: 00/52879 (2000-09-01), None
patent: WO 00/52879 (2000-09-01), None
Jouppi et al., “Tradeoffs in Two-Level On-Chip Caching”, Computer Architecture, 1994, Proceeding the 21st Annual International Symposium on, Apr. 18-21, 1994, pp. 34-45.
“ATLAS I: A Single-Chip, Gigabit ATM Switch with HIC/HS Links and Multi-Lane Back-Pressure,” Katevenis, et al., IPC Business Press LTD., Long, GB, vol. 21, No. 7-8, Mar. 30, 1998, XP004123981, 5 pages.
“An Introductory VHDL Tutorial: Chapter 1—An Introduction and Background,” 1995, Green Mountain Computing Systems, XP002212233, 2 pages.
International Search Report for 02253533.0-1525, Oct. 11, 2002.
SiByte, “Target Applications,” http://sibyte.com/mercurian/applications.htm, Jan. 15, 2001, 2 pages.
SiByte, “SiByte Technology,” http://sibyte.com/mercurian/technology.htm, Jan. 15, 2001, 3 pages.
SiByte, “The Mercurian Processor,” http://sibyte.com/mercurian, Jan. 15, 2001, 2 pages.
SiByte, “Fact Sheet,” SB-1 CPU, Oct. 2000, rev. 0.1, 1 page.
SiByte, “Fact Sheet,” SB-1250, Oct. 2000, rev. 0.2, 10 pages.
Stepanian, SiByte, SiByte SB-1 MIPS64 CPU Core, Embedded Processor Forum 2000, Jun. 13, 2000, 15 pages.
Jim Keller, “The Mercurian Processor: A High Performance, Power-Efficient CMP for Networking,” Oct. 10, 2000, 22 pages.
Tom R. Halfhill, “SiByte Reveals 64-Bit Core For NPUs; Independent MIPS64 Design Combines Low Power, High Performance,” Microdesign Resources, Jun. 2000, Microprocessor Report, 4 pages.
Pentium® Pro Family Developer's Manual, vol. 1:Specifications, Chapter 4, pp. 1-18, 1996.
“PowerPC 601,” RISC Microprocessor User's Manual, Revision 1, Motorola, Inc. 1993, p. 8-14.
Intel, “Pentium Processor Family User's Manual,” vol. 1: Pentium Processor Family Data Book, 1994, pp. 5-23 and 5-50.
Katevenis et al.; “ATLAS I: a single-chip, gigabit ATM switch with HIC/HS links and multi-lane back-pressure”;Microprocessors and Microsystems, IPC Business Press Ltd.; vol. 21, No. 7-8 Mar. 30, 1998; pp. 481-490.
Green Mountain Computing Systems; “An Introductory VHDL Tutorial: Chapter 1—Introduction and Background, Chapter 2—Structural Descriptions”; on line publication, http://www.gmvhdl.com/VHDL.html.
Chui Kwong-Tak A.
Desai Shailendra S.
Dobberpuhl Daniel W.
Hayter Mark D.
Garlick & Harrison & Markison
Harrell Robert B
LandOfFree
System on a chip for caching of data packets based on a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System on a chip for caching of data packets based on a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System on a chip for caching of data packets based on a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3958815