Method of reducing film stress on overlay mark

Details Method of reducing film stress on overlay mark Method of reducing film stress on overlay mark

2008-01-29

2008-01-29

Nguyen, Tuan H. (Department: 2813)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Having substrate registration feature

C438S462000, C438S975000

Reexamination Certificate

active

11715527

ABSTRACT:
An integrated circuit capable of operating despite a profile shift is disclosed. Overlay marks on the integrated circuit are surrounded by a trench that tends to relieve the effect of a profile shift caused by stress applied to the integrated circuit. The position of the overlay marks tends, therefore, not to be affected by the stress.

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