Pulse or digital communications – Transceivers – Transmission interface between two stations or terminals
Reexamination Certificate
2008-01-22
2008-01-22
Phu, Phuong (Department: 2611)
Pulse or digital communications
Transceivers
Transmission interface between two stations or terminals
C375S219000, C375S257000, C326S030000
Reexamination Certificate
active
10749429
ABSTRACT:
An integrated circuit (IC) device that has an analog front end with an I/O buffer is reset. The I/O buffer has a driver circuit to transmit a stream of information over a serial point to point link, and a receiver circuit to receive a stream of information over the link. Digitally-controllable transmission line terminations are provided for the driver and receiver circuits, respectively. A digitally-controllable reference signal level is also provided for the I/O buffer. A number of impedance matching compensation values are automatically calibrated against one or more reference resistors, by calibrating a first value and then a second value, and a third value. These calibrated values are automatically applied to set the reference signal level, driver termination, and receiver termination, respectively. Other embodiments are also described and claimed.
REFERENCES:
patent: 5910731 (1999-06-01), Polczynski
patent: 6812734 (2004-11-01), Shumarayev et al.
patent: 6836144 (2004-12-01), Bui et al.
patent: 2002/0101278 (2002-08-01), Schultz et al.
patent: 2002/0190746 (2002-12-01), Abrosimov et al.
Ravi Budruk, et al., “PCI Express System Architecture”, PC System Architecture Series, MindShare, Inc., Addison-Wesley copyright 2004, ISBN #0-3212-15630-7 (Contents, pp. vii-xxxvii; Part Three The Physical Layer—Chapter 11 Physical Layer Logic, pp. 397-451; and Chapter 12 Electrical Physical Layer, pp. 453-486).
“PCI Express™ Base Specification Revision 1.0a”, Apr. 15, 2003 (Incorporated Errata C1-C67 and E1-E4.17) PCI Express (Contents, pp. 3-8; and Section 4.2.7 Clock Tolerance Compensation through Section 4.2.8 Compliance Pattern, pp. 200-201).
Kotamreddy Sarath
Renaud Lyonel
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Phu Phuong
LandOfFree
Automatic impedance matching compensation for a serial point... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Automatic impedance matching compensation for a serial point..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Automatic impedance matching compensation for a serial point... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3938716