Operation circuit based on floating-point representation with se

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G06F 738

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active

049775340

ABSTRACT:
An operation circuit based on a floating-point representation system includes a first bypass line with respect to a shifter, and a second bypass line with respect to a two's complementer. When values of the exponent parts of two input operands are identical to each other, the mantissa part of one of the input operands bypasses the shifter, and is supplied to an ALU. In the other case, the mantissa of one of the input operands passes through the shifter, and is always supplied to the ALU. The mantissa of the other input operand is directly supplied to the ALU. When the values of the exponent parts are identical to each other, an output of the ALU passes through the two's complementer and is output as a final operation result. In other cases, the output of the ALU is directly supplied as the final operation result. The sign of the final operation result is determined by a sign discriminator.

REFERENCES:
patent: 4075704 (1978-02-01), O'Leary
patent: 4644490 (1987-02-01), Kobayashi et al.
patent: 4796218 (1989-01-01), Tanaka et al.
patent: 4827441 (1989-05-01), Someshwar et al.
patent: 4841467 (1989-06-01), Ho et al.
patent: 4866652 (1989-09-01), Chu et al.

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