Semiconductor device manufacturing: process – Making device array and selectively interconnecting – Rendering selected devices operable or inoperable
Reexamination Certificate
2008-09-30
2008-09-30
Lee, Hsien Ming (Department: 2823)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
Rendering selected devices operable or inoperable
C257SE21616
Reexamination Certificate
active
11668476
ABSTRACT:
A method of manufacturing a well pick-up structure of a non-volatile memory is provided. A substrate including a first conductive type well, device isolation structures and dummy memory columns is provided. Each of the dummy memory columns includes a second conductive type source region and a second conductive type drain region. A first interlayer insulating layer with an opening is formed over the substrate, and the opening exposes the two adjacent second conductive type drain regions and the device isolation structure between the two adjacent second conductive type drain regions. A portion of the device isolation structure exposed by the opening is removed, and then a first conductive type well extension doped region is formed in the substrate exposed by the opening. A well pick-up conductive layer is formed in the opening. Dummy bit lines electrically connecting the well pick-up conductive layer are formed over the substrate.
REFERENCES:
patent: 6483749 (2002-11-01), Choi et al.
patent: 2002/0175378 (2002-11-01), Choe et al.
patent: 2007/0080380 (2007-04-01), Chang
Wang Pin-Yao
Wong Wei-Zhe
Jianq Chyun IP Office
Lee Hsien Ming
Parendo Kevin A
Powerchip Semiconductor Corp.
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