Parallel execution processor and instruction assigning...

Electrical computers and digital processing systems: processing – Processing architecture – Long instruction word

Reexamination Certificate

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C712S203000, C712S215000, C712S216000

Reexamination Certificate

active

10686746

ABSTRACT:
The parallel execution processor100fetches a piece of instruction data. When the piece of instruction data includes only one instruction, the instruction decoding unit120assigns the one instruction to all the PEs. When the piece of instruction data includes two instructions, the instruction decoding unit120forms all the PEs into two groups, so as to assign one instruction to each group. By making it possible to execute, in parallel, not only one type of instruction but also instructions that are different from each other, it is possible to improve the utilization efficiency of the parallel execution processor100.

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Rymarczyk, James W, Coding Guidelines for Piplined Processors, Mar. 13, 1982, Architectural Support for Programming Languages and Operating Systems, 12-19.

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