Low capacitance wiring layout

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration

Reexamination Certificate

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C257S758000, C257S776000, C257SE23142, C257SE23151, C438S622000

Reexamination Certificate

active

11116181

ABSTRACT:
Integrated circuits having multi-level wiring layouts designed to inhibit the capacitive-resistance effect, and a method for fabricating such integrated circuits, is described. The integrated circuits have at least two planes of wiring adjacent to each other and extending in the same direction. One embodiment may further include a larger than normal insulator material between planes of wiring extending in one direction and at least one plane of wiring extending in a second direction transverse to the first direction. Each of the wiring channels in a wiring plane may be offset relative to a respective wiring channel in the next adjacent wiring plane which extends in the same direction.

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patent: 6143641 (2000-11-01), Kitch
patent: 6522011 (2003-02-01), Farrar
Mark T. Bohr,Interconnect Scaling—The Real Limiter to High Performance ULSI, IEEE, 1995.
P. Wrschka, J. Hernandez, G. S. Oehrlein, and J. King,Chemical Mechanical Planarization of Copper Damascene Structures, The Electrochemical Society, Inc.

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