Clock-less serial data interface using a single pin

Details Clock-less serial data interface using a single pin Clock-less serial data interface using a single pin

2008-01-01

2008-01-01

Liu, Shuwang (Department: 2611)

Pulse or digital communications

Receivers

C375S213000, C375S242000, C375S256000, C375S257000, C375S259000, C365S201000, C365S185180, C324S073100, 37, 37, C323S283000

Reexamination Certificate

active

10776154

ABSTRACT:
A data communication method for receiving digital data on a data terminal includes receiving data pulses having a first pulse separation to represent a first logical data value and a second pulse separation to represent a second logical data value, generating a voltage ramp signal, resetting the voltage ramp signal at a first delay after the leading edge of each data pulse, regenerating the voltage ramp signal at a first time period after the resetting of the voltage ramp signal, detecting the voltage value of the voltage ramp signal at the leading edge of each data pulse, and generating a data output signal associated with each data pulse. The data output signal has a first logical state when the voltage value of the voltage ramp signal is less than a threshold value and a second logical state when the voltage value of the voltage ramp signal is greater than the threshold value.

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