Prevention of latch-up in CMOS integrated circuits using Schottk

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357 15, 357 41, 357 86, H01L 2702

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active

045133093

ABSTRACT:
A complementary metal oxide semiconductor (CMOS) circuit is described incorporating Schottky barrier diodes in parallel with the source or drain of either the P or N channel transistors to reduce the minority current injected into the body at times the source or drain of either the N or P channel transistors are forward biased. The Schottky diode may be fabricated by making enlarged openings exposing both the body (substrate) and drain or source region and by using a metallization which may form an ohmic contact with the drain or source region and at the same time for a Schottky diode with the substrate. By incorporating Schottky barrier diodes parallel to the drain or source the P and N-type transistors are not current limited by the barrier height of only a Schottky diode acting as the source and at the same time minority current is not injected into the substrate or body at times the drain or source is forward biased. An input and output protection network is also described incorporating Schottky diodes.

REFERENCES:
patent: 4152717 (1979-05-01), Saton
patent: 4300152 (1981-11-01), Lepselter
patent: 4327368 (1982-04-01), Uchida

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