Semiconductor memory device having a stacked capacitor cell stru

Details Semiconductor memory device having a stacked capacitor cell stru Semiconductor memory device having a stacked capacitor cell stru

1991-05-17

1992-08-25

Hille, Rolf

357 41, 357 54, H01L 2968, H01L 2702, H01L 2934

Patent

active

051426390

ABSTRACT:
In a stacked capacitor cell structure of a semiconductor memory device, the MIM (metal-insulator-metal) capacitor to be used as a transfer gate comprises at least a unit stack of a first insulation film, a lower capacitor electrode, a capacitor gate insulation film, an upper capacitor electrode, another capacitor gate insulation film and an extension of the lower capacitor electrode. Thus, the surface area of the lower capacitor electrode can be enlarged without increasing the plane area exclusively occupied by memory cells. Moreover, with such a configuration, since the surface area of the lower capacitor electrode can be augmented without increasing the film thickness of the electrode, the technical difficulties that the currently known methods of manufacturing semiconductor memory devices with a stacked capacitor cell structure encounter are effectively eliminated and consequently troubles such as short-circuited lower capacitor electrodes become non-existent.

REFERENCES:
patent: 4953126 (1990-08-01), Ema
patent: 5021357 (1991-06-01), Taguchi et al.

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