Method of manufacturing a semiconductor device

Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material

Reexamination Certificate

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Details

C438S706000, C438S689000, C438S690000, C257SE21252, C257SE21275, C257SE21279

Reexamination Certificate

active

11370892

ABSTRACT:
Even though photolithography with a diameter of 0.20 μm or less is employed, a contact hole having a tapered shape with a required width including a positioning tolerance can be formed in a narrower gap between the gate electrodes. A method forms a minute contact hole between gate electrodes of a semiconductor device, which has a silicon dioxide film disposed at an upper layer of the semiconductor device and a BPSG film disposed below the silicon dioxide film. The BPSG film has gate electrodes therein, and no silicon nitride film is disposed on top and side surfaces of the gate electrodes, and no silicon nitride film is disposed above the gate electrodes. The silicon dioxide film is etched by a mixed gas of CF4, O2and Ar at a substrate temperature of at least 40° C. The BPSG film is etched by over-etching of the silicon dioxide film so that a W-like shape is formed in the BPSG film. Subsequently the BPSG film is etched by a mixed gas of C4F8, CH2F2and Ar without including CO gas and O2gas so that the contact hole between the adjacent gate electrodes has a forward tapered shape with a tapered angle of less than 90 degree.

REFERENCES:
patent: 6878612 (2005-04-01), Nagao et al.
patent: 7169682 (2007-01-01), Hirohama et al.
patent: 2002/0030174 (2002-03-01), Yamada et al.
patent: 2005/0170607 (2005-08-01), Hirohama et al.
patent: 0 536 968 (1993-04-01), None
patent: 05-102107 (1993-04-01), None
patent: 06-283460 (1994-10-01), None
patent: 2001-127039 (2001-05-01), None

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