System and method for minimizing DC offset in outputs of...

Details System and method for minimizing DC offset in outputs of... System and method for minimizing DC offset in outputs of...

2008-05-27

2008-05-27

Pascal, Robert J. (Department: 2817)

Amplifiers

With periodic switching input-output

C327S333000, C330S010000, C330S251000, C330S20700P

Reexamination Certificate

active

10862902

ABSTRACT:
An amplifier system receives an input signal and generating therefrom an amplified output signal. The amplifier system is recited as comprising an input stage and an amplifier stage. The input stage is configured to receive the input signal and provide a level-shifted signal that has an average signal level that is shifted in regards a level shift value. The amplifier stage is configured to receive the level-shifted input signal from the input stage and generate therefrom the amplified output signal. The level shift value being selected to minimize a DC offset in the amplified output signal at least when the amplifier system is initially powered on. Since the amplified output signal has a minimal or zero DC offset, the amplifier system avoids generation of undesirable noises when it is initially powered on.

REFERENCES:
patent: 6388514 (2002-05-01), King et al.

Affiliated with

Also associated with

Rating

System and method for minimizing DC offset in outputs of... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with System and method for minimizing DC offset in outputs of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for minimizing DC offset in outputs of... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3914606