Method and apparatus for testing semiconductor devices at speed

Details Method and apparatus for testing semiconductor devices at speed Method and apparatus for testing semiconductor devices at speed

1993-10-22

1996-06-04

Voeltz, Emanuel T.

Excavating

371 223, 371 224, 371 225, 375327, G01R 3126

Patent

active

055241140

ABSTRACT:
A method and apparatus for testing semiconductor devices at device operating speed for both proper combinational and timing logic functions with a standard low speed logic tester. A high speed phase-lock-loop system clock of the semiconductor device is frequency and phase locked to the lower speed logic tester clock. Test data is shifted into the semiconductor device at the test clock speed. Two controlled system clock pulses are utilized to clock the test data into the semiconductor devices. The first of these two pulses starts the test and the second ends the test. In this way, the combinational functions of the semiconductor devices are tested at the system operating speed.

REFERENCES:
patent: 3582633 (1971-06-01), Webb
patent: 4806879 (1989-02-01), Troxel
patent: 4876702 (1989-10-01), Lesko

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