Interconnect structure for TFT-array substrate and method...

Details Interconnect structure for TFT-array substrate and method... Interconnect structure for TFT-array substrate and method...

2007-10-23

2007-10-23

Parker, Kenneth (Department: 2815)

Liquid crystal cells, elements and systems

Particular structure

Interconnection of plural cells in parallel

C257SE51005, C257S758000, C257S449000, C438S609000, C349S187000

Reexamination Certificate

active

11470268

ABSTRACT:
An interconnect structure connecting two isolated metal lines in a non-display area of a TFT-array substrate. A first metal line is disposed on the substrate, covered with a first insulating layer. A second metal line is disposed on the first insulating layer and covered by a second insulating layer. ITO (indium tin oxide) wiring is disposed on the second insulating layer, electrically connecting the first and second metal lines. A passivation structure is disposed on the second insulating layer, with an opening therein to expose and surround the ITO wiring.

REFERENCES:
patent: 6198517 (2001-03-01), Ohori et al.
patent: 6362866 (2002-03-01), Yamazaki et al.
patent: 6466281 (2002-10-01), Huang et al.
patent: 6674093 (2004-01-01), Tanaka et al.
patent: 6934000 (2005-08-01), Ishii et al.

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