Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2007-10-09

2007-10-09

Tran, Michael T (Department: 2827)

Static information storage and retrieval

Addressing

Sync/clocking

C365S194000

Reexamination Certificate

active

11321876

ABSTRACT:
Disclosed herein is a semiconductor memory device for reducing an unnecessary current consumption occurred in an idle state or an active state. The semiconductor memory device includes a driving clock supply unit for supplying a driving clock during a read or a write operation of each bank; a delay unit for generating a read address or a write address in synchronization with the driving clock by delaying an address by a predetermined time based on one of an additive latency, a CAS latency and a combination thereof; and an output unit for latching the read address or the write address to output the latched signal as an internal column address.

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