Methods for reducing a thickness variation of a nitride...

Details Methods for reducing a thickness variation of a nitride... Methods for reducing a thickness variation of a nitride...

2007-10-16

2007-10-16

Sarkar, Asok Kumar (Department: 2891)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Having substrate registration feature

C257S797000, C438S975000

Reexamination Certificate

active

10998809

ABSTRACT:
A method for reducing a thickness variation of a nitride layer in a shallow trench isolation (STI) CMP process is provided, the method including forming an active region pattern in an alignment key region of a scribe lane where a device isolation film is formed at an ISO level, and forming a dummy active region pattern substantially adjacent to a vernier key pattern in the scribe lane during formation of the vernier key pattern, wherein the dummy active region pattern is spaced apart from the vernier key pattern by a known distance. Preferably, the active region pattern and the dummy active region pattern are formed prior to the STI CMP process.

REFERENCES:
patent: 5017514 (1991-05-01), Nishimoto
patent: 6703287 (2004-03-01), Fujiishi et al.
Hyuk Kwon et al., “WID Rnit Variation Improvements for HSS STI CMP Process Using Modified Scribe Lane Pattern Design”, Mat. Res. Sco. Symp. Proc., 2004, pp. K9.3.1-K9.3.6, vol. 816.

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